The present invention relates to a memory macro cell which is merged with, for example, a logic unit.
This application is based on Japanese Patent Application No. 10-330802, filed Nov. 20, 1998, the content of which is incorporated herein by reference.
FIG. 31 shows the configuration of a DRAM that is merged with a logic unit. On a semiconductor chip 10 is placed a logic circuit unit 11 that consists of a gate array or standard cells. In the center of the logic circuit unit 11, a memory macro 12 is placed which consists of macro cells by way of example. Further, an I/O unit 13, including input/output pads, is placed on the periphery of the chip 10. For example, a phase locked loop (PLL) circuit may be placed in the logic circuit unit 11.
When a memory macro having a large capacity of more than 1 Mbits is formed of a DRAM, it is difficult to use an automatic design technique to generate automatically a DRAM array of an arbitrary number of row and columns because the DRAM operational margin depends greatly upon capacitances associated with bit and word lines. For such a DRAM macro cell (hereinafter referred to as a DRAM macro), a technique has generally been used which arranges parts, such as memory arrays, which have been designed manually in advance contiguously by the number that satisfies a desired storage capacity.
The DRAM macro has a memory cell array and a pair of data lines (hereinafter referred to as a paired DQ line or paired DQ lines). The paired DQ line is used to transfer read data from the memory cell array to an input/output buffer and to transfer write data from the input/output buffer to a memory cell selected in the memory cell array. The larger the storage capacity of the DRAM macro, the longer the paired DQ line is. Thus, as the storage capacity of the DRAM macro increases, the delay time suffered by a data signal that is transmitted over the paired DQ line increases. At data read time, therefore, the time required for data read from a selected memory cell to be transferred over the paired DQ line to the input/output data buffer and then latched in that buffer also depends on the length of the paired DQ line. To prevent erroneous data latching, therefore, the input/output buffer has its latch timing delayed so as not to latch data from when data readout is started until the signal amplitude on the paired DQ line reaches a predetermined potential.
However, with the conventional DRAM macro, the delay time associated with the latch timing is fixed to suit the maximum storage capacity of the memory macro. For this reason, a unnecessarily long delay time has been set for a memory macro having a small storage capacity. Thus, such a DRAM macro as has a small storage capacity has a problem that the time required to read data becomes unnecessarily long.
The same problem arises at data write time. That is, at data write time, write data is transferred from the input/output buffer to the paired DQ line, then transferred from the paired DQ line to bit lines and written into a selected memory cell. Since a memory macro of large storage capacity has a large capacitance associated with paired DQ lines, a write pulse is rounded while data is being transferred over the paired DQ line, which makes the effective pulse width narrower. In view of this, in a memory macro of large storage capacity it is required to make the width of a write pulse larger than in the memory macro of small storage capacity.
However, the delay time introduced by a delay circuit that defines the write pulse width has conventionally been set long to provide for a memory macro of large storage capacity, which causes a problem in the case of a memory macro of small storage capacity in that the data write time becomes unnecessarily long.
Thus, since the conventional DRAM macro has its timing of reading/writing data fixed to provide for the implementation of a memory macro of large storage capacity, a problem arises in implementation of a memory macro of small storage capacity in that the data read/write time becomes unnecessarily long.